1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic products. More particularly, the present invention relates to planarizing methods for fabricating microelectronic products.
2. Description of the Related Art
Common in the art of microelectronic product fabrication is the use of planarizing methods such as chemical mechanical polish (CMP) planarizing methods. Planarizing methods provide advantages when fabricating microelectronic products insofar as planarizing methods often allow for fabrication of devices and structures which are not otherwise readily fabricated.
While planarizing methods are thus desirable and often essential when fabricating microelectronic products, planarizing methods are nonetheless not entirely without problems. In that regard, it is often difficult to provide planarizing methods with enhanced planarizing stop properties.
It is thus towards the goal of providing planarizing methods with enhanced planarizing stop properties that the present invention is directed.
Various methods have been disclosed for fabricating microelectronic products with desirable properties.
Included but not limiting among the methods are methods disclosed within: (1) Gonsiorawski et al., in U.S. Pat. No. 4,751,191 (a method for fabricating a solar cell product by providing a patterned hydrogenated silicon nitride layer as a mask layer when forming a grid electrode therein); and (2) Cathey et al., in U.S. Pat. No. 6,232,218 (a plasma etch method for fabricating a microelectronic product by employing a hydrogenated silicon nitride plasma etch stop layer when plasma etching a silicon oxide layer).
Desirable in the microelectronic fabrication arts are planarizing methods with enhanced planarizing stop properties for fabricating microelectronic products.
It is towards the foregoing object that the present invention is directed.